When writing data to a non-volatile memory, the data is typically first cached in a buffer and is then programmed to analog memory cells of the memory. Occasionally, a programming operation may fail and re-programming of the original data is required. Various methods for data re-programming following a programming failure are known in the art. For example, U.S. Pat. No. 7,945,825, whose disclosure is incorporated herein by reference, describes methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) loading an SRAM with user data; (3) if programming is successful, then flipping bits in the SRAM; and (4) if programming is not successful, reading data back from the array to the SRAM.
U.S. Pat. No. 7,924,628, whose disclosure is incorporated herein by reference, describes a cache programming operation which requires two SRAMs (one for the user and one for the array) that may be combined with a multi-level cell (MLC) programming operation which also requires two SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).